TSMC’s Estimated Wafer Prices Revealed: 300mm Wafer at 5nm Is Nearly $17,000
A blogger has published estimates of TSMC’s wafer costs and prices. Quite unsurprisingly, processing of wafers is getting more expensive with each new manufacturing technology as nodes tend to get more capital intensive. TSMC’s latest N5 (5nm) fabrication process appears to be particularly expensive on per-wafer basis because it is new, but its transistor density makes it particularly good for chips with a high transistor count.
RetiredEngineer, a well-known semiconductor blogger, has published a table with a calculation of TSMC’s sale price per hypothetical chip by node in 2020. The source of the table was not mentioned, but it probably comes from a recent report covering foundry business and makers of semiconductors.
The model is based on an imaginary 5nm chip the size of Nvidia's P100 GPU (610 mm2, 90.7 billion transistors at 148.2 MTr/mm2). As far as foundry sale price per patterned 300-mm wafer is concerned, the model takes into account such things as CapEx, energy use, depreciation, assembly, test and packaging costs, foundry operating margins, and some other factors. Meanwhile, the foundry sale price per chip also includes design costs, yet this number varies greatly from company to company and from node to node (i.e., design costs of a 610 mm2 5nm are different for different companies and implementation of a 610 mm2 chip varies from node to node due to different design rules and IP), so it should be taken with a grain of salt.
According to the estimates, TSMC sells a 300mm wafer processed using its N5 technology for about $16,988. By contrast, the world’s largest contract maker of semiconductors charges around $9,346 per 300mm wafer patterned using its N7 node as well as $3,984 for a 300mm wafer fabbed using its 16nm or 12nm technology.
There are several factors that make TSMC’s N5 node so expensive to use today. Firstly, TSMC started to produce 5nm chips several months ago and the fab as well as equipment it uses have not depreciated yet. Secondly, N5 heavily relies on usage of extreme ultraviolet lithography and can use it on up to 14 layers. According to ASML, one EUV layer requires one Twinscan NXE step-and-scan system for every ~45,000 wafer starts per month. Each EUV tool is believed to cost about $120 million and these scanners are rather expensive to run, too. Given TSMC’s volumes, it needs loads of such scanners for its N5 technology. Therefore, it will take some time before TSMC depreciates the fab and equipment it uses for N5.
But even at current costs it makes a great sense for makers of highly-complex chips to use TSMC’s leading-edge process because of its high transistor density as well as performance. Based on the numbers provided, it costs $238 to make a 610mm2 chip using N5 and $233 to produce the same chip using N7. At 16/12nm node the same processor will be considerably larger and will cost $331 to manufacture. At N5, the chip will not only be relatively small (at 610mm2 to be more precise), but it will also run 15% faster at a given power or consume 30% less power at a given frequency when compared to N7.
According to TSMC, its N5 has a lower defect density than N7 at the same time of its lifespan, so chip designers can expect that eventually N5-based chips will yield better than N7-based ICs in general. The latter is something to expect given the fact that N5 replaces DUV multi-patterning with EUV single patterning.
One thing to keep in mind with such a comparison between nodes is that while it is based on data from TSMC as well as the semiconductor industry in general, the actual numbers have never been confirmed by the Taiwanese giant, so they may not be a 100% accurate.
From 90 nm to 20 nm, the price of the wafer didn't increase as much, however, starting from 16/12 nm node(s), TSMC has seen costs per wafer, and other costs increase exponentially. For example, just compare the 10 nm wafer price of $5992 with the price of a 5 nm wafer which costs an amazing $16988. This is more than a 180% price increase in just three years, however, the cost per transistor is down as you get around 229% higher density in that period, making TSMC actually in line with Moore's Law. That is comparing Transistor density (MTr / mm²) of52.51 million transistors for the 10 nm nodeand 173 million transistors per mm² of the 5 nm node.
In brief: CSET (The Center for Security and Emerging Technologies) has published a new report, titled “AI chips: What they are and why they matter,” in which they calculate the sales price of silicon wafers. They found that TSMC’s 5nm node requires exceptionally expensive wafers that aren’t cheaper on a per-chip basis than 7nm chips. However, they still believe that 5nm chips are a popular purchase.
According to CSET’s model, a single 300 mm wafer built on the 5nm node costs approximately $16,988. A similar wafer built on the 7nm node reportedly costs $9,346.
Using a theoretical ~600 mm2 die, approximately equal in size to the Nvidia GA102 GPU used inside the RTX 3080 and RTX 3090, the per-chip costs of each die were calculated to be $233 and $238, for the 7nm and 5nm nodes, respectively.
CSET: Calculation of foundry sale price per chip in 2020 by node
|Mass production year and quarter||2015 Q3||2017 Q2||2018 Q3||2020 Q|
|Capital investment per wafer processed per year||$11,220||$13,169||$14,267||$16,746|
|Capital consumed per wafer processed in 2020||$993||$1,494||$2,330||$4,235|
|Other costs and markup per wafer||$2,990||$4,498||$7,016||$12,753|
|Foundry sale price per wafer||$3,984||$5,992||$9,346||$16,988|
|Foundry sale price per chip||$331||$274||$233||$238|
Reproduced from CSET report "AI Chips: What Are They and Why They Matter"
The foundry sale price per wafer is calculated as the sum of the "other costs and mark-up per wafer" and the "capital consumed per wafer processed in 2020," or in other words, the sum of the profit margins, assembly cost, and estimated development cost. Consequently, this is an average value for only a small window of time; TSMC will be varying the actual sales price above and below this value depending on long-term strategies and market conditions.
Nevertheless, this is a rigorously estimated value and a good baseline for the actual sales price of the wafers. From it, we can deduce that 5nm products, including the processors used in the next generation of Apple handsets, will not be cheaper than existing products.
The high costs of 5nm production are largely a consequence of their novelty, and in time, they’ll become cheaper. However, the 5nm node does require some unique treatments that make it more expensive than older nodes. It is heavily reliant on EUV (extreme ultraviolet lithography) techniques, and reportedly, each EUV tool costs $120 million. A single wafer can have up to fourteen EUV layers applied to it.
Despite the cost, the 5nm node is a promising one. At the same power consumption as a 7nm chip, a 5nm one will run 15% faster. At the same performance level, a 5nm chip will consume 30% less power than a 7nm one. And the 5nm node is reported to have better yield rates, too.
Image credit: Laura Ockel
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Rising Wafer Cost
It looks the calculation assumes a 600m2 die at 7nm and then factors in the shrink in die size moving to 5nm. If so the calculation is optimistic because it’s assuming the 1.84 logic density going from 7nm to 5nm applies to 100% of the 600mm2 die area which of course it wouldn’t, density increase for memories will be less and mixed signal interfaces will probably have no significant gain. The real increase in chip cost would therefore be greater.
On the other hand if it was a 600mm2 die at 7nm you’d only get one per reticle and if you could benefit from the full 1.84 density increase you’ve be at around 220mm2, just about small enough to fit two die images on each reticle making the per transistor cost lower at 5nm…
Of course the general conclusion is right assuming the wafer costs are correct, just don’t illustrate it with a 600mm2 die at 7nm, instead just note that the logic density improvement from 7nm to 5nm broadly matches the wafer price uplift.
Per wafer cost 7nm
Apple A13 & Beyond: How Transistor Count And Costs Will Go Up
Today we've got a detailed report for Apple's future processor design and costs. The Cupertino tech giant became the second company in the world to introduce gadgets with TSMC's advanced 7nm processors. Given Apple's penchant for taking its time before being confident that new technologies will withstand the brunt of mass usage, the introduction of an iPhone with 7nm came at the right time.
The effects of the move to 7nm are compounded by the fact that Samsung has completely dropped the ball with its in-house Exynos processors. Estimates today from IBS Research hint at the future for the iPhone, as we move towards 5nm in 2020 should current reports bear fruit. Take a look below for more details.
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TSMC's 5nm Process Might Allow The Apple A14* To Have 10.5 Billion Transistors, Cheaper Cost Per Transistor And $12,500/Wafer
The era of 7nm has allowed Apple to cram 7 Billion transistors inside the A12. This is an increase in density as the chip's surface area is 4.39 mm2 less than its predecessor (87.66 mm2 for the A11; 83.27 mm2 for the A12). Today's research estimates suggest that with the A14, Apple will match the A12X's transistor count on a smaller die (on 85 mm2 , as compared to the A12X's 122 mm2)
Such performance on an iPhone will provide developers with a lot of leeway, but at the same time, it will increase the iPhone's price. Costs all across the board for 5nm's development will escalate. A wafer, for instance, will cost $12,500 in the largest increase since the jump from 16nm to 10nm. The boost in performance owing to more transistors offered by 5nm's advanced etching, however, will be offset by reduced yield. As opposed to 7nm's 545.65, NDPW (Net Die per Wafer) for 5nm will go down to 530.25 from 7nm's 545.65.
As these figures are not directly from TSMC or Apple, do not expect them to materialize precisely. However, the end result will nevertheless deviate only slightly from the estimates. TSMC has commenced 5nm risk production, and the fab promises a 15% performance gain on a Cortex A72 core. Samsung is expected to implement GAAFET on 3nm after an agreement with IBM while TSMC's plans for the node are unknown. GAAFET can squeeze 30 Billion transistors on 50 mm2, making today's numbers look childish.
As you'll see above, R&D costs for 5nm are through the roof. They've increased by 50% over 7nm, and now require significant capital infusions at every phase of the process design. Software implementations, for example, will now cost $225 million for 5nm as opposed to $145 million for 7nm. These costs will naturally be shared by every company that hopes to utilize TSMC's next-generation process, yet the same companies (including Apple) will be forced to increase prices. These higher prices will not serve Apple well, as stiff competition in Asia will cut right through its operating margin.
Looking at the numbers, unless there's a major breakthrough, performance for the iPhone will plateau in the near future. It's at this time that Apple's current move into services will matter the most. If the Cupertino tech giant waters this plant carefully by then, it will have fully capitalized on the iPhone's singular advantage over Android a.k.a a strong iOS ecosystem. For now, let's hope more details for the 2019 iPhone lineup leak soon.
Download: iOS 15.0.2 for iPhone and iPad Released [IPSW Links]
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The author has no position in any of the stocks mentioned. WCCF TECH INC has a disclosure and ethics policy.
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